Cisco ASR 9006 Manuel d'utilisateur Page 3

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Presentation_ID
3
FIC
CPU BITS/DTI
Fully Distributed
Architecture for High
Performance and High Multi-
dimensional Control Plane
Scale
Data forwarding is fully
distributed on the line cards
Control plane split among RSP
and LC CPU (same type of CPU as
RSP)
L2 protocols, BFD, CFM, Netflow
runs on the LC CPU for high scale
True Modular OS for HA and
Operational Simplicity
Micro-kernel based, true modular OS
High availability and System stability
SW patch granularity for operational simplicity
Line Card
ASR 9000 System Architecture “At-a-Glance”
Switch Fabric
FIA
CPU
RSP
Active-Active Switch Fabric
Guarantee “0” packet loss during RSP failover
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