Cisco ASR 9006 Manuel d'utilisateur Page 12

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Presentation_ID
13
NP0PHY
NP2PHY
NP3PHY
NP1PHY
FIA0
CPU
NP4PHY
NP6PHY
NP7PHY
NP5PHY
FIA1
Example: A9K-8T
B0
NP: Network Processor
Main forwarding ASIC
L2 & L3 forwarding,
features (QoS, ACL, etc),
control plane policing,
mcast replication, etc
10Gbps bi-directional with
features applied
30Gbps raw bandwidth
CPU (same as RSP)
Program HW forwarding tables
Distributed Control planes
SW switched packets
Inline Netflow
FIA: Fabric Interface ASIC
Provide non-blocking data
connection to switch fabric
Internal system queues/VoQ
Intelligent mcast replication
B: Bridge FPGA
Provide non-blocking data
connection between NP and FIA
Internal System queues
Intelligent mcast replication
10G PHY for one 10G
port, or 10x1G port
Line Card Architecture Hardware Components
Note, Bridge FPGA provide non-blocking
connection between NP and the FIA. Functionally it
does the HW conversion due to different interface
format on NP and FIA. It’s part of the switch fabric
connection. To make it logically simple, it will be
removed from the remaining slides.
B1
B0
B1
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